DM9161A DM9161B
Q
About pin 11~13：Op1 op2 op3 to be set "1 1 1", that means auto-negotiation for all ability. In fact,it only can transmit 10/full or 10/half when link partner set 10/full or 10/half not on normal
auto-negotiation.
A
Please check the voltage of pin 11~13 that is really high voltage firstly.
(DM9161A)-2
Q
How to fix transmission speed to 10MBit?
A
you have to note 3 points by call PHY-MII function NetNIC_PhyRegWr () as follows,
1. Set MII_ANAR valued reg_val = 0x0461, for PHY 10M Full/half TX-ability operating with H/W Flow-control,
2. clear-bit MII_BMCR valued reg_val &= ~0x2000, for 10M PHY-Mode and
3. set-bit MII_BMCR valued reg_val != 0x1200, for PHY compatibility by set auto-negotiation enable
For example:
**********************************************
reg_val = 0x0021 | 0x0041 | 0x0400;
NetNIC_PhyRegWr (AT91C_PHY_ADDR, 4, reg_val, perr);
reg_val = 0x3100;
reg_val &= ~BMCR_SPEED100;
reg_val |= BMCR_ANENABLE;
reg_val |= 0x0200;
reg_val &= ~0x0100; // disable *Full-duplex mode default
NetNIC_PhyRegWr (AT91C_PHY_ADDR, 0, reg_val, perr);
*******************************************************
Note*: PHY did not fix Full/half duplex mode while power-on initialization
(DM9161A)-3
Q
We try to read register DSCSR (address: 17) but failed. MDC is about 480ns for each clock cycle. From this waveform, You can find Preamble, SFD(01), OP code(10), PHY address (00000), register address (10001), then there is no turn around zero state and data is always keep in high state. I try to read several other registers. I always get the same result. Do you have any comment for me?
A
Please check the circuit for PHY Address. In our suggestion circuit, the PHY address is 00001. If your PHY address setting is not the same with your circuit. Please modify and try again.
(DM9161A)-4
Q
Could you please let us know recommended Crystal manufacturers?(Background of this question) A customer (their crystal manufacturer) says as follows.It looks like that Table6-1 is rather not standard specifications.It is near to particular spec.
A
SIWARD (http://www.siward.com.tw/en/)
Q
what is the meaning of "Case Capacitance”?
A
Case Capacitance = (Holder Capacitance or Shunt Capacitance) All crystals have small electrodes that connect the crystal to the package pins. The electrodes form a shunt capacitance in parallel with the crystal's LC model, as shown in Figure 1. Depending on the crystal's size and package, the holder capacitance can vary.
Figure 1. Generic crystal model (fundamental mode).
(DM9161A)-5
Q
"tTXs" is setup time (12ns (Min)) of TXD, TXEN, TXER to TXCLK High (rise).We think that it is necessary timing for the relation between TXD and TXCLK.However, "tTXOD"(25ns (Max)) is specified, too.As "tTXs" is specified, it looks like that "tTXOD" is not indispensable.Is "tTXOD" necessary? Why "tTXOD" is specified?
A
Yes, it is necessary. It must be measured from DM9161
Q
According to customer,Their MAC device output TXD with 7ns (Max) delay after receiving TXCLK High (rise).As TXCLK Cycle Tyme is 40ns(Typ), TXD setup time is 33ns (=40-7) to next TXCLK High (rise) for DM9161A.Is this estimation correct?
A
Yes. It is ideal estimation, if tTXOD=7ns (MAX) is measured from DM9161A. In fact, such as trace effect between MAC and DM9161 will add delay time.
Q
At above case, can their MAC device be used with DM9161A?
A
Yes. From 7ns (MAC spec.) to 25ns (DM9161A spec.), it still has margin for no ideal effect.
Q
If answer of Q3 is YES, which is the correct reason, A) or B)?
A) TXD setup time: 33ns (=40-7) to next TXCLK High (rise) > "tTXs"(12ns (Min).
B) MAC device output TXD with 7ns (Max) delay after receiving TXCLK High (rise) < "tTXOD"(25ns (Max))
A
A) and B) are all correct reasons that all follow DM9161A SPEC.
Q
tTXOD (25ns) + tTXs (12ns) =37ns, tTXC 40ns .The difference is 3ns. (=40-37), How do we think this 3ns difference?
A
tTXOD (25ns) + tTXs (12ns) =37ns < tTXC (40ns), that is under spec.
(DM9161A)-6
Q
Why pins 11, 12 and 13 are low for 500ms after reset?
A
The pulled-low for 500ms is using to show reset complete.
(DM9161A)-7
Q
In RMII mode, Should we use 50 MHz Crystal to X1 and X2 pin and use X2 pin as 50 MHz output pin for MAC side reference clock using. Right??
A
In RMII Mode, please use OSC. 50MHz and connect the output of OSC 50MHz to XT2 and MAC side for reference clock.
Q
Could we use the same X’tal or OSC clock source in both modes??
A
No, MII mode use crystal or OSC 25MHz.RMII mode use OSC 50MHz
Q
In both mode, Could we use OSC as our clock source and only use X1 as our Input pin??
A
Yes. But we suggest using XT2 better.
Q
Can DM9161BIEP operate as a stand alone device without host initialization through the two wire management interface?
(DM9161B)-2
A
If only use MDC and MDIO to connect CPU, data can't be transmitted and received.
Q
We would like to have the PHY be on default configured as Auto Nego mode and PHY ID be configurable. Can it be done and what setting is required?
A
a. Auto Nego mode:
Pin 11, 12, 13 internal default are "pulled high =(U)" for 5.7 Table of Media Type selection.
(OP2 OP1 OP0 =1, 1, 1 =Auto-negotiation Enable all Capability) of page8,9 of datasheet.
Please refer the circuit as attachment.
If LED aren’t be used, just only float pin11, 12, and 13 (because pulled high internally).
b. PHY ID
Please refer page25 of datasheet for register 02 and 03.
(DM9161B)-3
Q
Pin 1, 2, 9 should be measured 1.8V as datasheet listed.
But we measured that is 2.1V…….
A
Please check as follows and test again.
a. 3.3V
b. Pin48=1.24V
c. Pin 47=GND
d. Badgap resistance between Pin 47 and 48 =6.8K (1%)
Please refer page12 of datasheet as follows.
1. Pin12 (SPEED LED): Low active (Pulled Up internally)
2. Pin13 (Link/active LED): Low active (Pulled Up internally)
(DM9161B)-4
Q
When pin 14 is pulled down, how to work with Pin12 (SPEED LED), Pin13 (Link/active LED), Pin14 (cable connection LED).
3. Pin14 (cable connection LED): High active (Pulled Down internally)
(DM9161B)-5
Q
If we want to replace 9161A with DM9161B, what do we need to note?
A
a. Auto Nego mode:
1. Hardware :
You can replace DM9161A with DM9161B directly.
But one thing you need to know is that pin 1, 2, 9 (Analog Receiver/transmit Power Output) of DM9161A is 2.5V and DM9161B is 1.8V.
|
Model No.
|
DM9161A
|
DM9161B
|
|
Analog Receiver/transmit Power Output
|
2.5V
|
1.8V
|
2. Software:
If you need to check the PHY ID in your software driver, please note that
PHY ID is different between DM9161A and DM9161B.
Please refer the datasheet about PHY ID identifier Register #2 (PHYID2)-03
|
Model No.
|
DM9161A
|
DM9161B
|
|
VNDR_MDL(Bit Name)
|
001010
|
001011
|
(DM9161B)-6
Q
In DM9103 +DM9161 RMII Circuit that RX_ER don't be use?
A
According to DM9161B used in MAC or Switch.(MAC need RX_ER/ SWITCH don’t need)
(DM9161B)-7
Q
Can the 1.8V of the transformer be supplied by the outside LDO?
A
Yes, it can be provided by outside LDO and just float the pin 1, 2 and 9 of DM9161B.